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ETC 5057 GP 84 R335 PLCC20
The ETC5057/ETC5054 family consists of A-law and µ–law monolithic PCM
CODEC/filters utilizing the A/D and D/A conversion architecture shown in
the block diagram below, and a serial PCM interface. The devices are
fabricated using doublepoly CMOS process. The encode portion of each
device consists of an input gain adjust amplifier, an active RC
pre-filter which eliminates very high frequency noise prior to entering a
switched-capacitor band-pass filter that rejects signals below 200 Hz
and above 3400 Hz. Also included are auto-zero circuitry and a
companding coder which samples the filtered signal and encodes it in the
companded A-law or µ–law PCM format.
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